1. Field of the Invention
The present invention relates to a plasma display panel driving method, a plasma display panel driver circuit, and a plasma display device, and more particularly, to a plasma display panel driving method, a plasma display panel driver circuit, and a plasma display device which are suitable for use when a high definition of display image is required.
2. Description of the Related Art
Plasma display devices mainly comprising a plasma display panel (PDP) are advantageous over conventionally widespread displays such as CRT (Cathode Ray Tube), liquid crystal displays, and the like in many aspects including a thin profile, a flickering-free feature, a large display contrast ratio, the ability to provide relatively large screens, a high response speed, the ability to emit multiple colors by use of selfluminous fluorescent materials, and the like. For this reason, the plasma display devices are being widely employed in recent display devices for use with computers, color image display devices, and the like.
The plasma display devices are classified into an AC type which has electrodes (scanning electrodes, discharge sustain electrodes, and data electrodes) covered with a dielectric layer, and is indirectly operated in an alternating current discharge state, and a DC type which has electrodes exposed to a discharge space and is operated in a direct current discharge state. The AC type plasma display devices are further classified into a memory operation type which utilizes memories of display cells for its driving, and a refresh operation type which does not utilizes such memories. The luminance of a plasma display device is proportional to the number of times of discharges, i.e., the number of repetitions of pulse voltages. The foregoing refresh type is mainly used for a plasma display device having a small display capacity because its luminance is lower as the display capacity is larger.
Next, a representative structure of the AC type PDP will be described.
This type of PDP, for example, as shown in FIG. 1, comprises a front substrate (first substrate) 1 and a back substrate (second substrate) 2 disposed in opposition to each other, and a discharge gas space 3 formed between these substrates. The front substrate 1 comprises a first insulating substrate 4, a scanning electrode 5, a discharge sustain electrode (also referred to as a “common electrode,” and hereinafter called the “sustain electrode) 6, a discharge gap 7, a dielectric layer 8, and a protection layer 9. The first insulating substrate 4 is made of a transparent material such as soda line glass or the like. The scanning electrode 5 and sustain electrode 6 are disposed in parallel to each other in a row direction H on the inner surface of the first insulating substrate 4, and are also formed opposite to each other across the discharge gap 7, to make up a pair of row electrodes (i.e., surface discharge electrode pair).
The scanning electrode 5 is comprised of a transparent electrode 5A and a bus electrode (trace electrode) 5B. The transparent electrode 5A is made of ITO (Indium Tin Oxide, transparent conductive thin film) or the like. The bus electrode 5B is made of a metal material such as Al (aluminum), Cu (copper), Ag (silver), or the like, and is formed to overlap a portion of the transparent electrode 5A for reducing the resistance of the transparent electrode 5A. The sustain electrode (common electrode) 6 in turn is comprised of a transparent electrode 6A and a bus electrode (trace electrode) 6B. The transparent electrode 6A is made of ITO or the like, similar to the transparent electrode 5A, while the bus electrode 6B is made of a metal material similar to that of the bus electrode 5B, and is formed to overlap a portion of the transparent electrode 6A for reducing the resistance of the transparent electrode 6A. The dielectric layer 8 is made of lead containing flint glass or the like for covering the scanning electrode 5 and sustain electrode 6. The protection layer 9, which is made of MgO (magnesium oxide) or the like, protects the dielectric layer 8 from a discharge.
On the other hand, the back substrate 2 comprises a second insulating substrate 12, a data electrode (also called the “address electrode”) 13, a dielectric layer 14, partitions 15, and a fluorescent material layer 16. The second insulating substrate 12 is made of a transparent material such as soda lime glass or the like. The data electrode 13 is made of Al (aluminum), Cu (copper), Ag (silver), or the like, and is formed in a column direction V perpendicular to the row direction H on the inner surface of the second insulating substrate 12. The dielectric layer 14 is made of lead containing flint glass or the like for covering the data electrode 13. The partitions 15, which are made of lead containing flint glass or the like, are formed in the column direction V for defining respective display cells. Then, the discharge gas space 3 is ensured by the partitions 15, such that a single or a mixture of discharge gases such as He (helium), Ne (neon), Xe (xenon) and the like is filled in the discharge gas space 3. The fluorescent material layer 16 is formed over regions which cover the bottom surfaces and wall surfaces of the partitions 15, and is divided into a red fluorescent material layer, a green fluorescent material layer, and a blue fluorescent material layer for converting ultraviolet rays generated by discharging the discharge gas into visible light P. Then, the display cells as shown in FIG. 1 are arranged in the row direction H and column direction V in a matrix form to provide the PDP 10.
The front substrate 1 and back substrate 2 are fixed in opposition to each other across a gap of approximately 100 μm, and have their peripheries hermetically sealed by a sealing material. The second insulating substrate 12, which forms part of the back substrate 2, is formed with a vent hole at a predetermined location, and a ventilation pipe, not shown, is attached to the outer surface of the insulating substrate 12 in alignment to the vent hole under a hermetically sealed state. The end of the ventilation pipe opposite to the end attached to the insulating substrate 12 is initially opened, such that the ventilation pipe is connected to an evacuation/gas filling device. Then, after the discharge gas space is evacuated to a vacuum by the evacuation/gas filling device, a discharge gas is filled into the discharge gas space. After the discharge gas has been filled, the ventilation pipe is chipped on by overheating to close the open end. In this way, the discharge gas space is filled with the discharge gas to complete the PDP 10. In the plasma display device which mainly comprises the PDP 10 as described above, one pixel is comprised of three display cells (red: R, green: G, and blue: B display cells) for a color display, while one pixel is comprised of one display cell for a monochrome display.
FIG. 2 is a diagram showing the layout of the electrodes of the PDP 10 which make up a main portion of an AC memory operation plasma display device of three-electrode surface discharge type.
As shown in FIG. 2, in this PDP 10, pairs of row electrodes comprised of scanning electrodes 21 (51, 52, 53, . . . , 5n) and sustain electrodes 22 (61, 62, 63, . . . , 6n) (common electrodes) run in parallel with one another in the row direction H on the inner surface of the front substrate 1 in FIG. 1. Also, column electrodes comprised of data electrodes 23 (131, 132, 133, . . . , 13m) (address electrodes) run in the column direction V on the inner surface of the back substrate 2 such that they are perpendicular to the row electrodes. Then, display cells 24, . . . , 24 are formed at respective intersections of these row electrodes with the column electrodes. The display cells 24, . . . , 24 are arranged in the row direction H and column direction V in a matrix form, and one display cell 24 has one each of the scanning electrode 21, sustain electrode 22, and data electrode 23. Therefore, the total number of display cells which make up one screen of the PDP 10 amounts to nm, where n is the number of pairs of row electrodes comprised of the scanning electrodes 21 and sustain electrodes 22, and m is the number of column electrodes comprised of the data electrodes 23.
FIG. 3 is a diagram for explaining the principle of a gradation display method used in the PDP 10 of FIG. 1. The horizontal axis represents the time, while the vertical axis represents numbers, not shown, of the scanning electrodes in the PDP.
As shown in FIG. 3, in the PDP 10, one frame period (for example, 16.7 ms, and also referred to as “one TV field”) is divided into eight sub-fields SF1, SF2, . . . , SF8 which are weighted based on gradation levels, and these sub-fields are further divided into an addressing discharge period (also referred to as the “scanning period”) and a discharge sustain period. Shading in each addressing discharge period represents a timing at which a scanning pulse is applied to each scanning electrode. When the scanning pulse and a display data pulse applied to the data electrode are added simultaneously, a write discharge is produced. A patterned portion (discharge sustain period) in FIG. 3 represents a period in which the display cells emit light for display.
In these discharge sustain periods, a discharge sustain pulse is alternately applied to the scanning electrode and sustain electrode. A discharge cell in which a discharge is produced during an addressing discharge period emits light at an intensity in accordance with the length of the discharge sustain period. Since the eight discharge sustain periods in FIG. 3 have their lengths in a ratio of 1:2:4:8:16:32:64:128, an image in 256 gradation levels (0-255) is displayed by combining light emissions in these discharge sustain periods. Also, the overall luminance is determined in an associated sub-field by the number of the discharge sustain pulses in the discharge sustain period. The number of times of light emissions in the overall discharge sustain period is increased as the discharge sustain pulse has a higher frequency in the discharge sustain period, resulting in a higher light emission luminance. However, as the frequency of light emission pulses is higher, the PDP 10 consumes more power.
FIG. 4 is a diagram showing exemplary driving waveforms in one sub-field in FIG. 3. In periods 1-5, a variety of driving pulses are applied to any electrodes. In the following, the PDP driving operation will be described with reference to FIG. 4.
Period 1 is a priming period Tp in which a priming discharge is produced for helping produce discharges in all display cells without fail. In the priming period Tp, the scanning electrode 5 is applied with a positive saw-tooth priming pulse Ppr-s, while the sustain electrode 6 is simultaneously applied with a negative rectangular priming pulse Ppr-c, resulting in a priming discharge produced in a discharge space near an electrode gap (discharge gap 7) between the scanning electrode 5 and sustain electrode 6 in each and every display cell to generate active particles for helping produce the discharge in the display cells. Then, negative and positive wall charges stick to the scanning electrode 5 and sustain electrode 6, respectively. The priming pulse Ppr-s has a peak value equal to a priming voltage Vp, while the priming pulse Ppr-c has a peak value equal to a ground level. The priming discharge in this event involves producing a faint discharge at the time a discharge start voltage is exceeded by a potential difference between the priming pulses Ppr-s and PPr-c applied to the scanning electrode 5 and sustain electrode 6, respectively, and repeating the faint discharges to exhibit a weak discharge form.
Period 2 is a priming erasure period Tpe in which a priming erasure discharge is produced for reducing the wall charges sticking on the scanning electrode 5 and sustain electrode 6. If the all charges remain as sticking in the priming period Tp (period 1), a sustain discharge can be produced in the next discharge sustain period Tc even in those discharge cells (display cells which should not be essentially displayed) in which a write discharge (also referred to as an “addressing discharge”) is not produced in the next addressing discharge period Tp (period 1), possibly resulting in an erroneous display. Therefore, the priming erasure period Tpe is provided in order to prevent the erroneous display as mentioned. In the priming erasure period Tpe, the scanning electrode 5 is applied with a negative saw-tooth priming erasure pulse Ppe-s which slowly falls, causing the wall charge to decrease as mentioned above. The priming erasure pulse Ppe-s presents a waveform which slowly decreases in the negative direction toward the scanning electrode 5. The priming erasure pulse Ppe-s has a peak value equal to a priming erasure voltage Vpe.
Period 3 is an addressing discharge period Ts in which a write discharge is produced for selecting display cells. In the addressing discharge period Ts, the scanning electrode 5 is applied with a scanning base pulse Pb, and is also applied with a negative rectangular scanning pulse Psc which falls down from the potential of the scanning base pulse Pb. Simultaneously, the data electrode 13 is applied with a positive rectangular display data pulse Pd, causing a write discharge to be produced in selected discharge cells. After the end of the scanning pulse Psc, a positive charge sticks to the scanning electrode 5, while a negative charge sticks to the sustain electrode 6 by the scanning base pulse Pb in display cells which emit light in a subsequent discharge sustain period. The scanning pulse Psc has a peak value equal to the ground level, while the display data pulse Pd has a peak value equal to the data voltage Vd. The write discharge is produced only at an intersection of the scanning electrode 5 applied with the scanning pulse Psc with the data electrode 13 applied with the display data pulse Pd. Then, wall charges stick to display cells in which the write discharge was produced, while no wall charges stick to display cells in which the write discharge was not produced.
Period 4 is a discharge sustain period Tc, in which a sustain discharge is produced for displaying only those display cells in which the write discharge was produced. In the discharge sustain period Tc, the sustain electrode 6 and scanning electrode 5 are alternately applied with positive rectangular sustain pulses Psus-c and Psus-s, respectively, from the sustain electrode 6 to repeatedly produce the sustain discharges. The sustain pulse Psus-c has a peak value equal to a sustain voltage Vs, while the sustain pulse Psus-s has a peak value equal to the ground level. In this event, since wall charges remain sticking in discharge cells in which the write discharge was produced in the addressing discharge period Ts, the sustain discharge is produced at the time a discharge start voltage is exceeded by a sum voltage of the wall charge voltage caused by the wall charge and a voltage caused by the positive sustain pulse Psus-c (applied first to the sustain electrode 6 as mentioned above). When the sustain discharge is produced, a wall charge sticks to cancel out the voltages applied to the sustain electrode 6 and scanning electrode 5. Consequently, negative and positive wall charges stick to the sustain electrode 6 and scanning electrode 5, respectively. Then, since the positive sustain pulse Psus-s is next applied to the scanning electrode 5, a sustain discharge is produced at the time the discharge start voltage is exceeded by a sum voltage of the voltage caused by the sustain pulse Psus-s and the voltage caused by the wall charge. Subsequently, such sustain discharges are repeated. The luminance level of the PDP is determined by the number of times of the sustain discharges in the discharge sustain period Tc.
Period 5 is a sustain erasure period Tce in which a sustain erasure discharge is produced for reducing the wall charges sticking on the scanning electrode 5 and sustain electrode 6 in the discharge sustain period Tc. In the sustain erasure period Tce, the scanning electrode 5 is applied with a negative saw-tooth sustain erasure pulse Pse-s which slowly falls down, causing the wall charge to decrease as mentioned above. The sustain erasure pulse Pse-s has a peak value equal to an erasure voltage Vpe. In the foregoing manner, the driving operation terminates in one sub-field, followed by a like driving operation in the next sub-field.
Other than the plasma display device described above, this type of techniques has been described, for example, in the following documents.
In a plasma display panel driving apparatus described in Laid-open Japanese Patent Application No. 11-65516 (page 6, FIG. 13) (Patent Document 1), a voltage applied to a scanning electrode gradually decreases in a write period when a discharge is produced to select discharge cells in which a sustain discharge is produced.
In a plasma display panel driving method described in Laid-open Japanese Patent Application No. 2002-140032 (page 4, FIGS. 1, 2), a potential applied to a scanning electrode during a write period is gradually reduced to compensate for an electric field in a discharge space, which has been lost due to a reduction in a wall charge during the write period, to realize a stable write discharge and a reduction in data voltage.
However, the conventional plasma display device described above has the following problems.
Specifically, the state of the wall charge within a cell immediately before the addressing discharge period Ts in FIG. 4 is such that a positive charge (+) deposits on the sustain electrode 6 and address electrode 13, while a negative charge (−) deposits on the scanning electrode 5, as shown in FIG. 5. During a write, the scanning electrode 5 is sequentially applied with the scanning pulse Psc, while the display data pulse Pd is applied only to the address electrode 13 which is positioned opposite to a location at which light is emitted in the appropriate scanning electrode 5. As a result, a discharge is produced between the scanning electrode 5 and addressing electrode 13 only in display cells which are applied with the two types of the aforementioned pulses, and this discharge triggers a discharge between the scanning electrode 5 and the sustain electrode 6 to form a wall charge required for a sustain discharge (a positive charge on the sustain electrode 5 and a negative charge on the sustain electrode 6), as shown in FIG. 6, causing the selected discharge cell to emit light during the discharge sustain period Tc.
On the other hand, as shown in FIG. 1, no wall charge required for the sustain discharge is formed in a display cell which is not applied with the display data pulse Pd. However, a scanning electrode which is scanned in a later turn by the scanning pulse Psc involves a longer time from the formation of the wall charge immediately before the addressing discharge period Ts shown in FIG. 4 to the application of the scanning pulse Psc, a weak erroneous discharge can be produced during this time between the scanning base pulse Pb and the display data pulse Pd output to select a display cell before the scanning line. In this event, as shown in FIG. 8, the negative charge on the scanning electrode 5 and the positive charge on the address electrode 13 are reduced to cause a shortage of the wall charges on both electrodes, possibly resulting in a failure of a write discharge between the scanning electrode 5 and address electrode 13, even if the scanning pulse Psc is applied, to lead to a resulting failure in the formation of the wall charge required for the sustain discharge and in light emission of the display cell.
The weak erroneous discharge produced between the scanning electrode 5 and the address electrode 13 is produced because active particles generated in Period 1 and Period 2 in FIG. 4 set up a state which facilitates a discharge. When a sustain discharge has been produced in the sub-field immediately before the sub-field concerned (preceding sub-field), the active particles generated in Period 1 and Period 2 are more activated to further facilitate the weak erroneous discharge. Since the active particles generated by the sustain discharge in the preceding sub-field increases as discharges are produced a larger number of times, the weak erroneous discharge is more likely to be produced between the scanning electrode 5 and the address electrode 13 when the sustain discharges are produced a larger number of times in the preceding sub-field. To prevent this state, the scanning base pulse Pb must be set at a higher voltage before the scanning pulse Psc is applied to the scanning electrode 5 in the addressing discharge period Ts, thereby making the weak erroneous discharge less likely to be produced.
On the other hand, in a display cell in which the scanning electrode 5 is applied with the scanning pulse Psc, and the address electrode 13 is applied with the display data pulse Pd, a sufficient potential difference must be ensured between the scanning electrode 5 and the sustain electrode 6 to form a wall charge required for a sustain discharge. Since the voltage applied to the sustain electrode 6 is always constant in the addressing discharge period Ts, the scanning base pulse Pb applied to the scanning electrode 5 must be set lower in order to form a sufficient wall charge for a sustain discharge. In this way, it is desired to vary the voltage of the scanning base pulse Pb before and after the application of the scanning pulse Psc applied to the scanning electrode 5 in the addressing discharge period Pb. With the scanning base pulse Pb set at a single voltage as before, a sufficient voltage setting margin cannot be ensured due to temperature-induced variations in a discharge voltage of the panel, resulting in limitations on a voltage range in which the scanning base pulse Pb can be set.
Furthermore, in cases where a drive waveform excluding the priming period Tp is utilized, the weak discharge between the scanning electrode and address electrodes in the previous subfield may not possibly be erased in the reset period of the subsequent subfield, resulting in a failure of light emission of the display cells in the subsequent field.
For example, as shown in FIG. 9, a limited range has been provided for setting the voltage of the scanning base pulse Pb. Specifically, since a discharge condition varies due to the temperature on the panel of the PDP 10, a lower limit (Vbwmin) of the voltage level of the scanning base pulse Pb is determined by a range in which the weak erroneous discharge is suppressed between the scanning electrode 5 and the address electrode 13 before scanning. An upper limit Vbwman of the level of the scanning base pulse Pb, on the other hand, is determined by a range in which the formation of a wall charge required for the sustain electrode 6 after scanning is facilitated. Thus, the level of the scanning base pulse Pb can be set irrespective of the temperature on the panel in a narrow range (96-100 V) surrounded by a dotted line in FIG. 14, providing no margin for the setting range. A measure to this problem may be to control the level of the scanning base pulse Pb in response to the temperature on the panel, but is difficult to implement because the temperature on the panel differs from one display cell to another, and it is difficult to detect the varying temperature without delay. This results in a problem of a degraded definition in displayed images.
The plasma display driving apparatus described in Patent Document 1 differs from the present invention in the driving method because the voltage applied to the scanning electrode gradually decreases during a write period in Patent Document 1. Likewise, the plasma display panel driving method described in Patent Document 2 differs from the present invention in the driving method, because the voltage applied to the scanning electrode gradually decreases during a write period, as is the case with Patent Document 1.